Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s Catapult High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerPro product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.
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Case Studies & White Papers
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|*Modeling and Synthesizing Large Ratio Rate Adapters||Application Note||Data Type||Catapult|
The file contains an example design and application note detailing the design of a 37/50 rate adaptor that can be applied to any large ratio rate conversion. It includes the appnote and source code example with a simple testbench.
|*RTL Power Reduction & High Level Synthesis Report 2013||May 2013||White Paper||PowerPro|
This report covers trends in the area of low power design and C based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends.
|*How to Maximize the Verification Benefit of High Level Synthesis with SystemC (HLS #4) - Webinar||November 2013||Video||Catapult|
In this 50 minute webinar, Calypto will cover a verification approach that leverages SystemC simulation and High Level Synthesis (HLS) to reduce the RTL verification effort by 50%. The SystemC designs used in an HLS flow typically simulate 100-1,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. This webinar describes how to write a bit-accurate SystemC design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL. (Recorded Live 11/5/2013).
|*Techniques for Reducing RTL Power at Various Levels (RTL #4) - Webinar||November 2013||Video||PowerPro|
The focus of this webinar will be on techniques for power reduction at the System and RTL. Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs are part of meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield.
|*RTLパワー削減および高位合成レポート 2013||December 2013||Presentation||PowerPro|
今年の年次報告は、世界各地の調査を基に、1) RTLパワー削減、および 2) 高位合成の2つのセクションを設けています。この調査は2012年12月に実施され、648名のSoC、IC、 FPGA設計者から回答を得ました。エンジニアならびにエンジニアリング･マネージャより得たこの包括的なフィードバックを解析する事により、当社はこの2つのテクノロジ･エリアに対する重要なトレンドをより明確に把握することができます。
|*Optimizing SystemC/C++ Hardware Architectures Through HLS (HLS #5) - Webinar||January 2014||Video||Catapult|
Next to numerical precision, hardware architecture has the biggest impact on RTL quality generated by high level synthesis (HLS). In this 50 minute webinar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in HLS. Webinar will focus on C++ and SystemC code examples on different hardware architectures and the effect on the final implementation.
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|How to Maximize Power Savings in your RTL: Theory and Practice||May 13||10:00 AM PST|
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