Use SystemC or C++ to automatically create verified, power ready RTL.
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Used guided or automatic optimization to reduce RTL power by up to 60%.
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Verify RTL without the need for vectors or time consuming simulation.
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About Calypto

Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s CatapultTM High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerProTM product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLECTM family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.

Upcoming Events

Name Date Time Location
Register for In-Depth Presentations, Demos, and Tutorials Presented by our Engineers & CustomersJune 8-10, 201510:00AM - 6:00PM

Register early to ensure availability

Power Regression flow for Soft IPsMonday June 8th10:30AM - 11:30AM

ROOM: 101


Ritesh Agrawal - Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India 
Ritesh Agrawal, Ankur Krishna, Kshitij Bajaj and Chanpreet Singh from Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India
Minimizing SOC Power Consumption With Power Efficient IPs and Associated TechniquesMonday June 8th11:30AM - 12:00PM

ROOM: 101 SESSION 2 - IP TRACK: Minimizing SOC Power Consumption With Power Efficient IPs and Associated Techniques

Speakers: Lluis Paris - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA
Aditya Mukherjee - Microsoft Corporation, Mountain View, CA
Shankar Krishnamoorthy - Mentor Graphics Corp., Fremont, CA
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India
Drew Wingard - Sonics, Inc., Milpitas, CA

Cooley's DAC Troublemaker PanelMonday June 8th3:00PM - 4:00PM

ROOM: 310

Moderator: John Cooley - Deepchip
Come watch the EDA troublemakers answer the edgy, user-submitted questions about this year's most controversial issues!  It's an old style open Q&A from the days before corporate marketing took over every aspect of EDA company images. 

Sanjiv Kaul - Calypto Design Systems, Inc., 
Joe Sawicki - Mentor Graphics Corp., 
Gary Smith - Gary Smith EDA, 
Amit Gupta - Solido Design Automation, Inc., 
Jim Hogan - Vista Ventures, 
Anirudh Devgan - Cadence Design Systems, Inc., 
Dean Drako - IC Manage, Inc., 
Clock Domain Crossing Considerations with Deep Sequential Optimizations for Low PowerWednesday June 10th4:30PM - 6:00PM

ROOM: 105

SESSION 52 - DESIGNER TRACK: New Directions in Static and Formal Methods

Jianfeng Liu - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Jianfeng Liu, Mi-Suk Hong, Jung Yun Choi, Kyungtae Do, and SungHo Park from Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Mohit Kumar, Srihari Yechangunja, Vishnu Kanwar, Gagan Minocha, and Divya Parihar from Calypto Design Systems, Inc., Noida, India

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Our Customers

Recent Collateral

* = User Information Required Before Download

Title Type Product Highlight
*Google Develops WebM Video Decompression Hardware IP using Technology Independent Sources and High Level SynthesisWhite PaperCatapult

This paper presents the HLS methodology used to develop the VP9 G2 hardware decoder and explain how it supports the goals and strategies of the WebM project. It explains why the HLS approach makes design implementation and verification 50% faster than a traditional RTL design flow, and how it enables design teams with different end products to collaborate and contribute to the same IP. 

*High Level Synthesis Report 2014White PaperCatapult

This is Calypto’s sixth annual High Level Synthesis survey report. 750 SoC, IC, and FPGA design professionals responded to the survey. This year's emphasis is on verification.

*Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisWhite PaperCatapult

Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.

*Clock Domain Crossing Aware Sequential Clock GatingWhite PaperPowerPro

In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings — this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art twopass solution is leading to an almost complete loss of power savings.

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