Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s CatapultTM High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerProTM product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLECTM family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.
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|*Designing ASIC IP at Higher Level of Abstraction||White Paper||Catapult|
In order for HLS/HLV adoption to be possible, standardized corporate design flows for HLS coding style, linting, constraint-driven synthesis, and design build as well as structural and functional verification of C++ and SystemC code were required. This paper discusses some of the reasons why this new HLS/HLV flow gives companies like Qualcomm several advantages, summarizes the flow and its benefits, and describes how it can provide even more advantageous features in the near future.
|*Google Develops WebM Video Decompression Hardware IP using Technology Independent Sources and High Level Synthesis||White Paper||Catapult|
This paper presents the HLS methodology used to develop the VP9 G2 hardware decoder and explain how it supports the goals and strategies of the WebM project. It explains why the HLS approach makes design implementation and verification 50% faster than a traditional RTL design flow, and how it enables design teams with different end products to collaborate and contribute to the same IP.
|*High Level Synthesis Report 2014||White Paper||Catapult|
This is Calypto’s sixth annual High Level Synthesis survey report. 750 SoC, IC, and FPGA design professionals responded to the survey. This year's emphasis is on verification.
|*Closing Functional and Structural Coverage on RTL Generated by High Level Synthesis||White Paper||Catapult|
Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.
|*Clock Domain Crossing Aware Sequential Clock Gating||White Paper||PowerPro|
In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings — this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art twopass solution is leading to an almost complete loss of power savings.
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