Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s Catapult High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerPro product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.
|DVCon Luncheon: What is Needed to Drive Design Efficiency?||March 2||12:00 - 1:30 PM|
Double Tree Hotel, San Jose, CA
|DVCon - Poster Session||March 3, 2015||10:30 - 11:00 AM|
Title: Closing Functional and Structural Coverage on RTL Generated by HLS
Author: Bryan Bowyer from Calypto
Location: Gateway Foyer
|DATE||March 9-13, 2015|
Title: Clock Domain Crossing Aware Sequential Clock Gating
From Samsung: Jianfeng Liu, Mi-Suk Hong, Kyungtae Do,
From Calypto: Abhishek Ranjan, Manish
Location: Grenoble, FRANCE
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|*Optimizing SystemC/C++ Hardware Architectures Through HLS (HLS #5) - Webinar||January 2014||Video||Catapult|
Next to numerical precision, hardware architecture has the biggest impact on RTL quality generated by high level synthesis (HLS). In this 50 minute webinar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in HLS. Webinar will focus on C++ and SystemC code examples on different hardware architectures and the effect on the final implementation.
|*Reaching for Maximum Power Reduction - Webinar:||May 2014||Video||PowerPro|
Power is perhaps the most challenging design constraint in advanced SoC/IPs today. Designers need to meet specific power goals in order to enter and sustain in several market segments. We know that more that 80% of the final SoC/IP power is decided at the RT level. In this interactive webinar, we will discuss the various power reduction strategies available for RT Level engineers and how they can be utilized to provide convergence to the power goals of the project. We will then talk about how to enable these techniques at RT Level and what are the various trade-offs available. This webinar will feature Calypto's Low Power Platform which helps RTL designers achieve power convergence. (Recorded Live 5/7/2014).
|*High Level Synthesis Report 2014||November 2014||White Paper||Catapult|
This is Calypto’s sixth annual High Level Synthesis survey report. 750 SoC, IC, and FPGA design professionals responded to the survey. This year's emphasis is on verification.
|*Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis||March 2015||White Paper||Catapult|
Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.
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