Given the complexity of today’s SoCs, efficient power management requires a holistic approach where the control logic, data paths, and memories are analyzed together and optimized for both dynamic and static power. However, identifying memory-gating opportunities is beyond the scope of RTL synthesis tools. Power conscious designers try to analyze the registers for redundant accesses and look for conditions under which such accesses can be shut off. There is no single known method of achieving this, and designers mostly develop this expertise over time. Even so, the process can get very tedious and error prone without suitable assistance.

Memory vendors provide several capabilities to reduce leakage power in memories that are not in use, and various flavors of sleep modes are now available in embedded memories, but using these modes requires the creation of controllers to generate the sleep and wake signals. In addition, the leakage power savings gained during sleep mode must be greater than the dynamic power dissipation associated with transitioning the memory in and out of sleep mode. The memory must be in sleep mode for a minimum number of cycles to actually save power. Finally, creating the sleep mode control signals and ensuring that sleep modes are triggered only during periods when the memory is quiet for an extended period require analysis of the design functionality over multiple cycles.

In this webinar, Calypto will show how its patented sequential analysis technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory.

Have you ever wondered the difference between C++ and SystemC for high level synthesis (HLS)? This 50 minute webinar will provide a practical overview of the differences between the two most common ESL hardware description languages. The webinar will show side by side coding examples of the two languages for basic hardware concepts such as: hierarchy, IO, numerical precision and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult Synthesis), Calypto is uniquely placed to discuss the differences between the two languages.

In this 50 minute webinar, we will cover the basics of designing for hardware with each language, covering what you can, and can’t do:

*    Bit-accurate datatypes

*    Architecture design

*    Interfacing

*    Hierarchy

*    Verification

Analyzing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effectivewithout considering the sequential nature of the design and representative switching activity.