Calypto was founded in 2002 and our first product was SLEC (Sequential Logical Equivalence Checker). The core Calypto technology is deep sequential analysis. This patented technology has been applied to the verification domain with our SLEC product family. It was then applied to the power analysis and optimization domain with our PowerPro platform.
SLEC formally verifies that two sequentially different designs are functionally equivalent. SLEC relies on deep sequential analysis for complete proof of designs with complex states. SLEC ensures that any micro-architectural changes to the RTL blocks — such as merging or splitting flops, re-encoding states, re-pipelining, retiming, and clock gating — can be exhaustively verified. Our deep sequential analysis capability enables SLEC to also verify a system model written in C++/SystemC against an RTL design despite the sequential differences between them (different throughput and latency).
Analyzing and optimizing power at the RTL can significantly reduce power, but it is challenging, especially when done manually. The widely used practice of inserting, for instance, clock gating may not be very effective without considering the sequential nature of the whole design.
PowerPro achieves superior quality of results (QoR) because it performs an exhaustive deep sequential analysis of the design, finding all the power optimization opportunities for datapath, memories, and registers. The deep sequential analysis process is purely functional and does not rely on stimulus, such as FSDBs or VCDs files. This is the reason why the PowerPro platform can be deployed early in the design cycle even when realistic stimulus are not available for the design. If the designer provides stimulus, then PowerPro will take into account the stimulus only after the deep sequential analysis process; thereby reducing the logical expression to minimize area overhead and maximize power savings.
PowerPro performs an exhaustive deep sequential analysis to identify writes that are either unobservable downstream or have the same value in consecutive cycles. Gating of the first type of redundant writes is called Observability Based Clock Gating and the second type of redundant writes is called Stability Based Clock Gating.
Our PowerAdviser flow relies on deep sequential analysis to provide information for additional power savings that the user can realize through manual changes. By using this flow we have achieved considerable power reduction. Deep sequential analysis can help explore other power saving transformations; such as, flop sharing, flop cloning, reset optimization, and memory caches.
I would recommend reading PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations, a case study available for download on our webpage.
Other existing techniques, such as structural pattern matching, enable forwarding technique, simulation driven, or limited sequential analysis (e.g., register analysis one cycle before and after) do not provide a complete view of the whole design, which is necessary to find all the potential power optimizations.
Written by Jerome Bortolami, Senior Field Application Engineer at Calypto Design Systems.