| 05.20.2013 | Gary Smith EDA - What to See @ DAC 2013Gary Smith EDA - What to See @ DAC 2013 |
| 05.16.2013 | Low-Power/High-Performance Engineering - Lessons Learned In 4G LTELow-Power/High-Performance Engineering - Lessons Learned In 4G LTE |
| 05.16.2013 | Chip Design - Raising the Bar for Power OptimizationChip Design - Raising the Bar for Power Optimization |
| 05.16.2013 | EDACafe - Sanjiv Kaul: Calypto and HLS to seize the dayEDACafe - Sanjiv Kaul: Calypto and HLS to seize the day |
| 05.09.2013 | Low-Power/High-Performance Engineering – Smarter Clock GatingLow-Power/High-Performance Engineering – Smarter Clock Gating |
| 05.09.2013 | Low-Power/High-Performance Engineering – What’s Missing In Low-Power VerificationLow-Power/High-Performance Engineering – What’s Missing In Low-Power Verification |
| 05.02.2013 | DeepChip - 648 engineers surveyed on RTL Power Reduction and HLS techniquesDeepChip - 648 engineers surveyed on RTL Power Reduction and HLS techniques |
| 05.01.2013 | SemiWiki – DAC: Calypto Insight PresentationSemiWiki – DAC: Calypto Insight Presentation |
| 04.12.2013 | Chip Design – Reducing Dynamic and Static Power in Embedded MemoriesChip Design – Reducing Dynamic and Static Power in Embedded Memories |
| 04.11.2013 | Low-Power/High-Performance Engineering – Optimizing IP For PowerLow-Power/High-Performance Engineering – Optimizing IP For Power |
| 04.09.2013 | Tech Design Forum – How AMD implemented efficient clock gating analysis for JaguarTech Design Forum – How AMD implemented efficient clock gating analysis for Jaguar |
| 03.24.2013 | Mercury News (SJ) - Sanjiv Kaul, Calypto Design SystemsMercury News (SJ) - Sanjiv Kaul, Calypto Design Systems |
| 03.14.2013 | EDACafe - Calypto Participates in Technical Session at DATE 2013: Detecting Isomorphisms in Logic DesignEDACafe - Calypto Participates in Technical Session at DATE 2013: Detecting Isomorphisms in Logic Design |
| 03.10.2013 | SemiWiki – Sanjiv Kaul: Is HLS About to Take Off?SemiWiki – Sanjiv Kaul: Is HLS About to Take Off? |
| 02.26.2013 | SemiWiki - High and Low: High Level Synthesis and Low PowerSemiWiki - High and Low: High Level Synthesis and Low Power |
| 02.14.2013 | DeepChip - Gary and Shawn school Brett on up-front vs ratable ESL sales modelsDeepChip - Gary and Shawn school Brett on up-front vs ratable ESL sales models |
| 02.06.2013 | SemiWiki – RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip!SemiWiki – RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip! |
| 02.04.2013 | Business Wire - Calypto Announces New President and CEO Sanjiv KaulBusiness Wire - Calypto Announces New President and CEO Sanjiv Kaul |
| 02.04.2013 | EE Times - Reducing power in AMD processor core with RTL clock gating analysisEE Times - Reducing power in AMD processor core with RTL clock gating analysis |
| 02.04.2013 | SemiWiki – Sanjiv Kaul is New CEO of CalyptoSemiWiki – Sanjiv Kaul is New CEO of Calypto |
| 01.30.2013 | SemiWiki – Dynamic/Leakage Power Reduction in MemoriesSemiWiki – Dynamic/Leakage Power Reduction in Memories |
| 01.07.2013 | EE Times - Making ESL power optimization a realityEE Times - Making ESL power optimization a reality |