A Webinar on the Latest Techniques for Power Optimization at RTLAbstract:Analysing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effectivewithout considering the sequential nature of the design and representative switching activity.
In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webinar will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization.
(recorded live 5/23/13)

It is a well-known fact that sequential clock gating is more global in nature and offers more power savings over combinational clock gating. However, sequential clock gating is very complex as it involves temporal analysis over multiple clock cycles as well as examination of the stability, propagation, and observability of signal values. Trying to do sequential clock gating manually is extremely difficult, if not impossible, as it requires keeping track of data values over multiple cycles. Recently, new tools have come to the market that automate the analysis and insertion of sequential clock gating. However, since sequential clock gating can potentially change the behavior of flops and memories, it introduces new verification challenges. Traditional verification methodologies such as simulation are not effective and are too time consuming. Sequential formal verification may very well be the answer.

In this webinar, Calypto will show the latest in sequential clock gating methodologies and its impact on the overall design flow. Latest sequential formal analysis, automated sequential clock gating, ECO and verification will be described.

In this webinar, Calypto will show how its patented sequential analysis technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory. (Recorded Live 02/12/2013)

A practical comparison between SystemC and C++ for High Level Synthesis

Have you ever wondered the difference between C++ and SystemC for high level synthesis (HLS)? This 50 minute webinar will provide a practical overview of the differences between the two most common ESL hardware description languages. The webinar will show side by side coding examples of the two languages for basic hardware concepts such as: hierarchy, IO, numerical precision and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult), Calypto is uniquely placed to discuss the differences between the two languages.

(Recorded Live 12/13/2012)

A Webinar on the Latest Techniques for Power Optimization at RTL
Abstract:Analysing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effectivewithout considering the sequential nature of the design and representative switching activity.

In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webinar will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization.

(recorded live 12/04/12)

Catapult Control Logic Demo Using C++.

Catapult Overview Demo Using C++.

Watch a demonstration of Catapult using SystemC.

This short video gives an overview of Catapult, explaining what it is, what it does and how design teams benefit from using it.

In this case study, Thomas Bollaert investigates a company's Return on Investment (ROI) for Catapult high level synthesis tool, and how they achieved a positive ROI within the first 12 months of Catapult usage.

In this primer, Shawn McCloud discusses best practices of high-level synthesis, and how the right coding style results in higher quality RTL and improved design reuse.

In this interview, Shawn McCloud discusses high-level synthesis and the three major trends driving adoption of this technology in design teams around the world.