Datasheets

* = User Information Required Before Download

Title Date Type Product Highlight
PowerPro Product Family DatasheetOn-GoingDatasheetPowerPro
Catapult Product Family DatasheetOn-GoingDatasheetCatapult
SLEC Product Family DatasheetOn-GoingDatasheetSLEC

White Papers

* = User Information Required Before Download

Title Date Type Product Highlight
*RTL Power Reduction & High Level Synthesis Report 2013May 2013White PaperPowerPro

This report covers trends in the area of low power design and C based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends.

*Implementing an Efficient RTL Clock Gating Analysis Flow at AMDJanuary 2013White PaperPowerPro

This paper provides an overview of how AMD used PowerPro to improve clock-gating efficiency, and shares the results and advantages of doing power analysis at the RTL stage rather than waiting until post-gate synthesis.

*Catapult LP for a Power Optimized ESL Hardware Realization FlowNovember 2012White PaperCatapult LP

This paper describes, in general, the Catapult® flow for exploring low power architectures, and it discusses in detail the low power optimization results achieved using the Catapult LP design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low power optimizations turned on. With low power optimizations on, Catapult uses the Calypto PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

*Memory Power Reduction in SoC Designs Using PowerPro MGWhite PaperPowerPro MG

Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50-70% of the power dissipation. We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories.

*Low Power RTL Report 2012April 2012White PaperPowerPro CG

This report covers trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey.

*High-Level Synthesis Report 20112011White PaperCatapult

This report analyzes the survey results of 1,133 engineers and engineering managers and identifies relevant emerging trends.

*7 Steps to Higher Productivity: STMicroelectronics HLS Flow for Complex IPsDecember 2010White PaperCatapult

This paper covers STMicroelectronic’s project, where they wanted to have a completed video processor IP design in silicon in time for CES 2010, so they could fully demonstrate the 3D graphic capability of their latest SOC.

*Advanced Algorithmic Evaluation for Imaging, Communication and Audio Applications - Eigenvalue Decomposition Using The Catapult® Algorithmic Synthesis MethodologyWhite PaperCatapult

This paper discusses the hardware implementation of “eigenvalue decomposition”. Therefore, we developed two effective algorithms in ANSI C++ to obtain eigenvalues and synthesized them with Catapult Synthesis to compare the area versus the number of cycles at the algorithm level, respectively.

*Designing High Performance DSP Hardware Using Catapult C Synthesis and The Altera Accelerated LibrariesWhite PaperCatapult

This paper covers the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL.

*Automating Sequential Clock Gating with PowerPro CGWhite PaperPowerPro CG

This paper describes sequential analysis and its application to clock gating. An example of sequential clock gating is given as well as a case study of reducing power in a digital signal correlation block using an automated RTL power optimization tool.

*Power Optimization of a Configurable Video Platform using PowerPro™ CGOn-goingWhite PaperPowerPro PA

With the proliferation of mobile multimedia devices, designers are challenged to provide the most advanced features to users while balancing the need to deliver the longest battery life possible.

*The PowerPro PowerAdviser flow: A Manual Use Mode for Applications that Require User InterventionOn-goingWhite PaperPowerPro PA

PowerPro CG provides an automated solution to reduce this part of the design time to essentially cut it down to just machine runtime per block. In this paper, we describe a flow that enables two use models; one is to enable the use of PowerPro for designers who must meet very aggressive performance goals and would therefore prefer to optimize their RTL manually, and the other is to enable users of the automated PowerProCG flows to get even better results by providing hints based on sequential analysis.

*Utilizing Clock-Gating Efficiency to Reduce Power in RTLWhite PaperPowerPro CG

With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are gated.

*Integrating Sequential Logic Equivalence Checking with the Cadence C-to-Silicon FlowOn-goingWhite PaperSLEC HLS

Specific emphasis is placed on the integration between SLEC and Cadence C to Silicon Compiler (CtoS).

*Sequential Equivalence Checking: A New Approach to Functional verification of Datapath and Control Logic ChangesWhite PaperSLEC RTL

This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.

*RTL Verification Without TestbenchesWhite PaperSLEC RTL

Sequential equivalence checking technology reduces testbench requirements, improving productivity and giving designers more opportunities to optimize their RTL designs. This paper traces the development of a DES encryption design to demonstrate the advantages of doing RTL verification without testbenches.

Case Studies

* = User Information Required Before Download

Title Date Type Product Highlight
*Reducing Power Consumption in a 20 million Gate Fiber Channel Switch SOCCase StudyPowerPro CG

This case study covers a leading networking company’s validation of PowerPro CG results on two projects. Based on these successes, they have incorporated PowerPro CG into their low-power design SoC design flow.

*Applying RTL Clock Gating to Reduce Power in Graphics Processors ChipsCase StudyPowerPro PA

This case study covers nVIDIA: “RTL power optimization is a critical step in our high-performance, low-power design methodology for PC graphics, visual computing and applications processors. PowerPro CG has shown substantial power savings on designs, including blocks already manually optimized for low power by RTL designers.”

*PowerAdviser: An RTL Power Platform for Interactive Sequential OptimizationsCase StudyPowerPro PA

In this Texas Instrument case study, an interactive sequential analysis flow called PowerAdviser is introduced. The flow provides information to the user about redundant clock toggles where the automatic tool has not been able to identify a suitable clock gating condition to save power.

*STARC Recommends PowerPro CG For RTL Power OptimizationCase StudyPowerPro CG

This case study discusses the evaluation criteria, process and results that led to the certification of PowerPro CG by STARC for its member companies.

*Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence CheckingCase StudySLEC

This case study describes the system-level design flow of a commercial graphics processing chip. In this flow, system models are developed to validate the arithmetic computation of video instructions and then used verify the RTL implementation using SLEC.

Technical Papers

* = User Information Required Before Download

Title Date Type Product Highlight
High-Level Synthesis Blue BookTechnical PaperCatapult

http://www.hlsbluebook.com/ 

This book provides a step-by-step approach to using C++ as a hardware design language, including an introduction to the basics of HLS using concepts familiar to RTL designers. Each chapter provides easy-to-understand C++ examples, along with hardware and timing diagrams where appropriate.

The book progresses from simple concepts such as sequential logic design to more complicated topics such as memory architecture and hierarchical sub-system design. Later chapters bring together many of the earlier HLS design concepts through their application in simplified design examples. These examples illustrate the fundamental principles behind C++ hardware design, which will translate to much larger designs. Although this book focuses primarily on C and C++ to present the basics of C++ synthesis, all of the concepts are equally applicable to SystemC when describing the core algorithmic part of a design.

On completion of this book, readers should be well on their way to becoming experts in high-level synthesis.

*DATE - A Semi-Canonical Form for Sequential AIGsFebruary 2013Technical PaperSLEC Product Family Overview

Calypto collaborated with UC Berkeley to develop an innovative way to detect isomorphisms within logic designs. Our work, presented in DATE 2013, describes a way to use simulation to quickly identify isomorphisms. 

*DATE - PowerAdviser: An RTL Power Platform for Interactive Sequential OptimizationsMarch 2012Technical PaperPowerPro PA

In this paper we present an interactive sequential analysis flow, PowerAdviser, which besides performing automatic sequential changes also provides information for additional power savings that the user realized through manual changes. Using this new flow they achieved dynamic power reduction up to 45% more than a purely automated flow.

Data Types

* = User Information Required Before Download

Title Date Type Product Highlight
AC DatatypesJune 2014Data TypeCatapult

Algorithmic C (AC) datatypes are a class-based C++ library that provides arbitrary-length integer, fixed-point, floating-point and complex data types. They enable algorithm, system and hardware designers to precisely model bit-true behavior in C++ specifications while accelerating simulation speeds by 10-200x faster versus alternate datatypes.

*Modeling and Synthesizing Large Ratio Rate AdaptersApplication NoteData TypeCatapult

The file contains an example design and application note detailing the design of a 37/50 rate adaptor that can be applied to any large ratio rate conversion. It includes the appnote and source code example with a simple testbench.

HLS 5 Webinar's Code FilesJanuary 2014Data TypeCatapult

This zipped folder contains the code files that were used throughout the HLS 5 webinar "Optimizing SystemC/C++ Hardware Architectures Through HLS". The folder contains 3 files: "Decimator", "Filters", and "Windowing". Decimator contains an example of a regular compute-discard architecture and a polyphase implementation. Filters contains examples of FIR filter architectures: Classic, Folded, and Circular buffer. Windowing contains an example high performance (streaming one-pixel-per-clock-cycle) Sobel edge detector.

日本語版

* = User Information Required Before Download

Title Date Type Product Highlight
Catapult ファミリ データシートOn-Going日本語版Catapult
PowerPro ファミリ データシートOn-Going日本語版PowerPro
SLEC ファミリ データシートOn-Going日本語版SLEC
*RTLパワー削減および高位合成レポート 2013December 2013日本語版PowerPro

今年の年次報告は、世界各地の調査を基に、1) RTLパワー削減、および 2) 高位合成の2つのセクションを設けています。この調査は2012年12月に実施され、648名のSoC、IC、 FPGA設計者から回答を得ました。エンジニアならびにエンジニアリング・マネージャより得たこの包括的なフィードバックを解析する事により、当社はこの2つのテクノロジ・エリアに対する重要なトレンドをより明確に把握することができます。

*CatapultとAltera社のAccelerated Libraryを使用した 高性能DSPハードウェア・デザインNovember 2013日本語版Catapult

従来のデザインフローは、C++のような高位言語でアルゴリズムの機能をモデル化し、これを手作業でRTLにコーディングしていました。この手作業によるRTL生成は時間がかかるだけでなく、エラーを発生しやすく、またバックエンドの配線遅延問題に影響を与えてしまいます。CatapultによるC++からの高位合成は、主にワイヤレス、ビデオ、画像処理など、非常に複雑で高い計算能力を必要とするアプリケーションで使用される、ASICハードウェア・サブシステムを構築するために使用されてきました。ASICで利用されてきたCatapultの機能とAltera社のAccelerated Libraryを組み合わせることにより、ANSI C++でモデル化したアルゴリズムから、FPGAハードウェア上で動作するように最適化されたRTLを迅速に生成することができます。さらに、このデザインフローを使用することで、C++からFPGA DSPブロックを直接生成し、高位合成制約を使用してバックエンドのタイミング問題を簡単に解決することが可能です。

*効果的なRTLクロック・ゲーティング解析フローを 用いたローパワー実装January 2013日本語版PowerPro

本稿では、AMD社がクロック・ゲーティングの効率を向上させるために、どのようにPowerProを使用したかの概要をご紹介し、ゲート合成を待たずにRTL段階で電力解析を行った場合の結果と利点をご説明します。

*生産性向上のための7つのステップ: STMicroelectronics社の複雑なIPのための高位合成フローDecember 2010日本語版Catapult

この論文は、STMicroelectronicsがCES2010でシリコンの状態で完全なビデオIPとして希望し、また実際に完全な3Dグラフィックス機能のデモを行うことができたプロジェクトに関するものです

*PowerPro MG による SoC 設計時のメモリ消費電力削減日本語版PowerPro MG

最新のSoCでは、メモリがシリコン面積の50%以上を占有し、消費電力に至っては50-70%を占めるまでになっています。従って、最適なメモリ・アーキテクチャを選択し、最適化されたメモリ・アクセスになるように確実に制御することは、あらかじめ仕様で決められたSoCの総消費電力量に収める上で非常に重要です。

*ローパワーESLハードウェア実現フローを 可能にするCatapult LPNovember 2012日本語版Catapult LP

本稿では、主にローパワー・アーキテクチャを検討するCatapult®フローをご紹介します。また、Catapult LPデザインフローを使用して達成した、ローパワー最適化結果について詳細に説明します。ケーススタディは、実際のお客様の設計を使用して行いました。設計は、Catapultのローパワー最適化を使用した場合と、使用しなかった場合の2種類の設定で合成しました。ローパワー最適化を使用した場合、Catapult LPは内蔵されているPowerPro®のRTLパワー最適化とパワー見積もりエンジンを適用します。

*PowerAdviser: インタラクティブな シーケンシャル・オプティマイゼーションを実現する RTLパワー・プラットフォーム日本語版PowerPro

今日の最新電子機器にとって電力は最も重要な懸案事項になってきています。クロック・パワーを削減するために、シーケンシャル・クロック・ゲーティングはコンビネーショナル・クロック・ゲーティングよりも使用されるようになっています。人手によるシーケンシャル・クロック・ゲーティングへの変更箇所の特定が複雑であるため、自動化ツールが一般的になってきています。しかし、これらのツールは常に、与えられたデザインや仕様の範囲内で動作するため、さらに可能な電力削減手段を示唆することはありません。本稿では、自動的にシーケンシャルな変更を行うと同時に、人手による変更を加えることで、さらに電力の削減を図れる情報を提供するインタラクティブなシーケンシャル・アナリシス・フローPowerAdviser をご紹介します。この新しいフローを使用することにより、単なる自動化フローと比較してダイナミック・パワーを最大45%削減しています。

*AC DatatypesOctober 2012日本語版Catapult

カリプト社が無償で提供するビット 精度のC/C++データタイプです。g++やVisual C++でコンパイルでき、SystemC比最大200倍の高速性を生かし、語長や固定小数点最 適化を迅速に行えます。データ型としては、任意の語長の符号付き、符号なし整数型、固定小数点型タイプがあり、 CatapultとSLECによる高位合成フローでもサポートされています。

Videos

* = User Information Required Before Download

Screenshot Date Type Product Title & Highlight
May 2014VideoCatapult *How to Maximize the Verification Benefit of HLS - Webinar

RTL verification is a major challenge in today’s design flow, requiring huge amounts of resources to satisfactorily validate the RTL code. By raising the abstraction level design and verification is performed, and automating the RTL creation, High Level Synthesis (HLS) can reduce the RTL verification effort by 50%. This because the C++ or SystemC designs used in an HLS flow typically simulate 1,000-10,000 times faster than RTL. This webinar describes how to write a bit-accurate C++ design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL.

Topics we will be covering are:
• Types of high level models 
• How to write and debug a synthesizable C++ model
• Coverage driven verification in the context of high level synthesis

(Recorded Live 5/15/2014).

May 2014VideoPowerPro *Reaching for Maximum Power Reduction - Webinar:

Power is perhaps the most challenging design constraint in advanced SoC/IPs today. Designers need to meet specific power goals in order to enter and sustain in several market segments. We know that more that 80% of the final SoC/IP power is decided at the RT level. In this interactive webinar, we will discuss the various power reduction strategies available for RT Level engineers and how they can be utilized to provide convergence to the power goals of the project. We will then talk about how to enable these techniques at RT Level and what are the various trade-offs available. This webinar will feature Calypto's Low Power Platform which helps RTL designers achieve power convergence. (Recorded Live 5/7/2014).

May 2014VideoPowerPro *How to Maximize Power Savings in your RTL: Theory and Practice (RTL #5) - Webinar

All IC designers want to minimize the power consumed by their designs.  Power is a key specification for IC designs.  It is critical for battery-operated designs and is becoming increasingly more important for all other designs. Power is a key differentiator in the competitive integrated circuit marketplace.  

There are a number of different techniques for reducing power consumption in digital integrated circuits. These start with the design of the process.  They include coarse grained approaches and fine grained methods.  Different techniques can often be combined, if done correctly.  


This webinar will survey some of the techniques to reduce power in digital IC designs.  Clock gating and power management techniques will be covered. (Recorded Live 5/13/2014).

January 2014VideoCatapult *Optimizing SystemC/C++ Hardware Architectures Through HLS (HLS #5) - Webinar

Next to numerical precision, hardware architecture has the biggest impact on RTL quality generated by high level synthesis (HLS). In this 50 minute webinar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in HLS. Webinar will focus on C++ and SystemC code examples on different hardware architectures and the effect on the final implementation.

Topics we will be covering are:
Fundamental filter architectures
Delay line implementation and windowing for efficient image processing
(Recorded Live 01/14/14).
HLS 5 Webinar's Code Files: http://goo.gl/Gzk13f

November 2013VideoPowerPro *Techniques for Reducing RTL Power at Various Levels (RTL #4) - Webinar

The focus of this webinar will be on techniques for power reduction at the System and RTL. Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs are part of meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield.

Traditionally, most automated power optimization tools have focused at gate-level and physical level optimizations. However, major power reductions are only possible by addressing power at the System and RTL levels. At these levels, it is possible to make the sequential modifications needed to reduce power and energy consumption via techniques like DVFS, power-gating, bus-data encoding, low power arithmetic architectures, memory-banking, sequential clock/memory gating and other micro-architectural techniques.
(Recorded Live 11/19/2013).

November 2013VideoCatapult *How to Maximize the Verification Benefit of High Level Synthesis with SystemC (HLS #4) - Webinar

In this 50 minute webinar, Calypto will cover a verification approach that leverages SystemC simulation and High Level Synthesis (HLS) to reduce the RTL verification effort by 50%. The SystemC designs used in an HLS flow typically simulate 100-1,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. This webinar describes how to write a bit-accurate SystemC design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL. (Recorded Live 11/5/2013).

July 2013VideoCatapult *How to Maximize the Verification Benefit of High Level Synthesis with C++ (HLS #3) - Webinar

In this 50 minute webinar, Calypto will cover a verification approach that leverages C++ simulation and High Level Synthesis (HLS) to reduce the RTL verification effort by 50%.

The C++ designs used in an HLS flow typically simulate 1,000-10,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. This webinar describes how to write a bit-accurate C++ design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL. (Recorded live 7/16/13).

April 2013VideoPowerPro *Impact of Sequential Clock Gating on Design Flow and Verification (RTL #3) - Webinar

It is a well-known fact that sequential clock gating is more global in nature and offers more power savings over combinational clock gating. However, sequential clock gating is very complex as it involves temporal analysis over multiple clock cycles as well as examination of the stability, propagation, and observability of signal values. Trying to do sequential clock gating manually is extremely difficult, if not impossible, as it requires keeping track of data values over multiple cycles. Recently, new tools have come to the market that automate the analysis and insertion of sequential clock gating. However, since sequential clock gating can potentially change the behavior of flops and memories, it introduces new verification challenges. Traditional verification methodologies such as simulation are not effective and are too time consuming. Sequential formal verification may very well be the answer.

In this webinar, Calypto will show the latest in sequential clock gating methodologies and its impact on the overall design flow. Latest sequential formal analysis, automated sequential clock gating, ECO and verification will be described.

February 2013VideoPowerPro *Dynamic/Leakage Power Reduction in Memories (RTL #2) - Webinar

In this webinar, Calypto will show how its patented sequential analysis technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory. (Recorded Live 02/12/2013)

March 2013VideoCatapult *How to Optimize for Power with High Level Synthesis (HLS #2) - Webinar
In this 50 minute webinar, Calypto will cover techniques to measure and reduce power in a High Level Synthesis (HLS) flow, starting from C++ or SystemC. 

For many designers, power optimization has become a key optimization target.  This webinar explains how moving to a more abstract source gives designers the ability to better optimize for power.  The webinar will cover both automated tool flows and manual techniques.  The automated tool flow focus on sequential clock gating, which uses both static state progression data and simulation vectors to disable registers that are not active.  The manual flow focuses on how to change the source code and HLS constraints to trade-off power with area, performance, and numerical precision. (Recorded Live 3/26/2013).

December 2012VideoPowerPro *Minimizing RTL Power Through Sequential Analysis (RTL #1) - Webinar

A Webinar on the Latest Techniques for Power Optimization at RTL
Abstract:Analysing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effectivewithout considering the sequential nature of the design and representative switching activity.

In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webinar will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization.

(recorded live 12/04/12)

December 2012VideoCatapult *Comparing C++ to SystemC for HLS (HLS #1) - Webinar

A practical comparison between SystemC and C++ for High Level Synthesis

Have you ever wondered the difference between C++ and SystemC for high level synthesis (HLS)? This 50 minute webinar will provide a practical overview of the differences between the two most common ESL hardware description languages. The webinar will show side by side coding examples of the two languages for basic hardware concepts such as: hierarchy, IO, numerical precision and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult), Calypto is uniquely placed to discuss the differences between the two languages.

(Recorded Live 12/13/2012)

October 2013VideoPowerPro *Dynamic/Leakage Power Reduction in Memories (RTL #2) - EU/IN Webinar Series

In this webinar, Calypto will show how its patented sequential analysis technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory. (Recorded Live 10/17/2013)

May 2013VideoPowerPro *Minimizing RTL Power Through Sequential Analysis (RTL #1) - EU/IN Webinar Series

A Webinar on the Latest Techniques for Power Optimization at RTLAbstract:Analysing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effectivewithout considering the sequential nature of the design and representative switching activity.
In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webinar will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization.
(recorded live 5/23/13)

VideoCatapult *Catapult Control Logic Demo Using C++

Catapult Control Logic Demo Using C++.

VideoCatapult *Catapult Overview Demo Using C++

Catapult Overview Demo Using C++.

VideoCatapult *SystemC Synthesis Demo

Watch a demonstration of Catapult using SystemC.

VideoCatapult *Catapult Synthesis Primer: Technology Overview

This short video gives an overview of Catapult, explaining what it is, what it does and how design teams benefit from using it.

VideoCatapult *Catapult Synthesis: A Return on Investment Case Study

In this case study, Thomas Bollaert investigates a company's Return on Investment (ROI) for Catapult high level synthesis tool, and how they achieved a positive ROI within the first 12 months of Catapult usage.

VideoCatapult *Best Practices of HLS

In this primer, Shawn McCloud discusses best practices of high-level synthesis, and how the right coding style results in higher quality RTL and improved design reuse.

VideoCatapult *HLS Primer

In this interview, Shawn McCloud discusses high-level synthesis and the three major trends driving adoption of this technology in design teams around the world.