Upcoming Tradeshows, Conferences and Webinars

Name Date Time Location/Registration
DACJune 8-10, 2015

Location: Moscone Center, San Francisco

IP TRACK: Power Regression flow for Soft IPsMonday June 8th10:30AM - 11:30AM

ROOM: 101

SESSION 1 - IP TRACK: Low Power IP

Speakers:
Ritesh Agrawal - Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India 
Authors:
Ritesh Agrawal, Ankur Krishna, Kshitij Bajaj and Chanpreet Singh from Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India
DESIGNER AND IP TRACK POSTER: Deep Submicron Multimillion Gates Implementation of FiberOptic Nonlinear Equalizers using High Level SynthesisTuesday June 9th4:30PM - 6:00PM

On the Exhibit Floor

SESSION 31.41 - DESIGNER AND IP TRACK POSTER: DAC Designer and IP Track Poster Session

Speakers:
Eudes P. Lopes - CPqD Research and Development, Campinas, Brazil
Authors:
Stenio M. Ranzini, Victor Parahyba, João B. Tardelli, Eduardo O. Schneider, Tomaz Vilela, Eudes P. Lopes, Jacklyn D. Reis, and Juliano F. Oliveira from CPqD Research and Development, Campinas, Brazil
Designer Track: Clock Domain Crossing Considerations with Deep Sequential Optimizations for Low PowerWednesday June 10th4:30PM - 6:00PM

ROOM: 105

SESSION 52 - DESIGNER TRACK: New Directions in Static and Formal Methods

Speaker:
Jianfeng Liu - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Authors:
Jianfeng Liu, Mi-Suk Hong, Jung Yun Choi, Kyungtae Do, and SungHo Park from Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Mohit Kumar, Srihari Yechangunja, Vishnu Kanwar, Gagan Minocha, and Divya Parihar from Calypto Design Systems, Inc., Noida, India