Upcoming Tradeshows, Conferences and Webinars

Name Date Time Location/Registration
DACJune 8-10, 2015

Location: Moscone Center, San Francisco

Register for In-Depth Presentations, Demos, and Tutorials Presented by our Engineers & CustomersJune 8-10, 201510:00AM - 6:00PM

Register early to ensure availability

Power Regression flow for Soft IPsMonday June 8th10:30AM - 11:30AM

ROOM: 101

SESSION 1 - IP TRACK: Low Power IP

Speakers:
Ritesh Agrawal - Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India 
Authors:
Ritesh Agrawal, Ankur Krishna, Kshitij Bajaj and Chanpreet Singh from Freescale Semiconductor, Inc., Noida, India
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India
Minimizing SOC Power Consumption With Power Efficient IPs and Associated TechniquesMonday June 8th11:30AM - 12:00PM

ROOM: 101 SESSION 2 - IP TRACK: Minimizing SOC Power Consumption With Power Efficient IPs and Associated Techniques

Speakers: Lluis Paris - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA
Aditya Mukherjee - Microsoft Corporation, Mountain View, CA
Shankar Krishnamoorthy - Mentor Graphics Corp., Fremont, CA
Saurabh Shrimal - Calypto Design Systems, Inc., Noida, India
Drew Wingard - Sonics, Inc., Milpitas, CA

Cooley's DAC Troublemaker PanelMonday June 8th3:00PM - 4:00PM

ROOM: 310

TRACK: EDA | TOPIC AREA: GENERAL INTEREST
Moderator: John Cooley - Deepchip
 
Come watch the EDA troublemakers answer the edgy, user-submitted questions about this year's most controversial issues!  It's an old style open Q&A from the days before corporate marketing took over every aspect of EDA company images. 

Panelists:
Sanjiv Kaul - Calypto Design Systems, Inc., 
Joe Sawicki - Mentor Graphics Corp., 
Gary Smith - Gary Smith EDA, 
Amit Gupta - Solido Design Automation, Inc., 
Jim Hogan - Vista Ventures, 
Anirudh Devgan - Cadence Design Systems, Inc., 
Dean Drako - IC Manage, Inc., 
Deep Submicron Multimillion Gates Implementation of FiberOptic Nonlinear Equalizers using High Level SynthesisTuesday June 9th4:30PM - 6:00PM

On the Exhibit Floor

SESSION 31.41 - DESIGNER AND IP TRACK POSTER: DAC Designer and IP Track Poster Session

Speakers:
Eudes P. Lopes - CPqD Research and Development, Campinas, Brazil
Authors:
Stenio M. Ranzini, Victor Parahyba, João B. Tardelli, Eduardo O. Schneider, Tomaz Vilela, Eudes P. Lopes, Jacklyn D. Reis, and Juliano F. Oliveira from CPqD Research and Development, Campinas, Brazil
Clock Domain Crossing Considerations with Deep Sequential Optimizations for Low PowerWednesday June 10th4:30PM - 6:00PM

ROOM: 105

SESSION 52 - DESIGNER TRACK: New Directions in Static and Formal Methods

Speaker:
Jianfeng Liu - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Authors:
Jianfeng Liu, Mi-Suk Hong, Jung Yun Choi, Kyungtae Do, and SungHo Park from Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Mohit Kumar, Srihari Yechangunja, Vishnu Kanwar, Gagan Minocha, and Divya Parihar from Calypto Design Systems, Inc., Noida, India