DAC 2013 Suite Sessions - Austin, TX
| Name | Date | Time | Location |
|---|---|---|---|
| AMD's Methodology Reduces Power by 20% (Customer Presentation) | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 3:00 PM CDT June 5th: 11:00 AM CDT |
| PowerPro RTL Analysis & Optimization Platform | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 9:00 AM CDT or 2:00 PM CDT June 4th: 9:00 AM CDT or 4:00 PM CDT June 5th: 12:00 PM CDT |
| Catapult ESL Synthesis & Verification Platform | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 11:00 AM CDT or 5:00 PM CDT |
| A Practical Comparison between C++ and SystemC for High Level Synthesis (Tutorial) | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 10:00 AM CDT June 5th: 3:00 PM CDT |
| Calypto Solution Overview | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 12:00 PM CDT June 4th: 1:00 PM CDT June 5th: 10:00 AM CDT |
| How to Use Deep Sequential Analysis to Minimize Power (Tutorial) | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 1:00 PM CDT June 4th: 3:00 PM CDT |
| Catapult LP - Low Power HLS | June 3 - 5 | Multiple Times | Calypto's Booth 1247 Register: June 3rd: 4:00 PM CDT June 4th: 12:00 PM CDT June 5th: 2:00 PM CDT |
| Renesas Formal Flow Cuts Verification Time (Customer Presentation) | June 4 | Multiple Times | Calypto's Booth 1247 Register: June 4th: 10:00 AM CDT (Presented in Japanese) June 4th: 2:00 PM CDT (Presented in English) |
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| Other Activities At DAC 2013 | June 3-5 | ||
| Session 3.41 Designer Track Poster Session 1: "Practical Consideration in a Sequential Power Optimization Flow" | June 4 | 12:30 PM - 1:30 PM CDT | Speaker: Udupi Harisharan, Cisco Systems & Uday Das, Calypto, Sr. Field Applications Engineer Location: Hall 5 |
| Session 7.11 Designer Track Poster Session 2: “Power Regression Methodology Reduces Dynamic Power by 20%” | June 5 | 12:30 PM - 1:30 PM CDT | Speaker: Steve Kommrusch, AMD, Sr. Fellow Design Engineer Location: Hall 5 |
| Insight Presentation – Reducing Design and Debug Time with Synthesizable TLM | June 5 | 2:00 PM - 4:00 PM CDT | Speaker: Bryan Bowyer, Calypto Design Systems Location: TBD |
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| Europe/India Webinar Series | |||
| Minimizing RTL Power Through Sequential Analysis – European/India Webinar | May 23 | 10:00 AM BST | UK (10:00 AM) | Europe (11:00 AM) | Finland (12:00 PM) | India (2:30 PM) |
| A Practical Comparison Between C++ and SystemC for High Level Synthesis – European/India Webinar | June 20 | 10:00 AM BST | UK (10:00 AM) | Europe (11:00 AM) | Finland (12:00 PM) | India (2:30 PM) |
| Dynamic/Leakage Power Reduction in Memories – European/India Webinar | September 12 | 10:00 AM BST | UK (10:00 AM) | Europe (11:00 AM) | Finland (12:00 PM) | India (2:30 PM) |