Upcoming Tradeshows, Conferences and Webinars

Name Date Time Location/Registration
SemiIsrael Expo - Track 2: Front-end Design & VerificationNovember 25th, 201414:00 - 14:20 (UTC+02:00)

SemiIsrael Expo - AVENUE
Airport city

Track 2: Front-end Design & Verification

Two Methodologies to Reduce Power Consumption in RTL Design
Richard Langridge

DVConMarch 2-4, 20152:30 PM - 7:30 PM

Booth #402

DVCon - Poster SessionMarch 3, 201510:30 - 11:00 AM

Title: Closing Functional and Structural Coverage on RTL Generated by HLS

Location: Gateway Foyer

DATEMarch 9-13, 2015

TitleClock Domain Crossing Aware Sequential Clock Gating
Authors: Mohit Kumar, Jianfeng Liu, Mi-Suk Hong, Kyungtae Do,
             JungYun Choi, Jaehong Park, Abhishek Ranjan, Manish
             Kumar and Nikhil Tripathi

Location: Grenoble, FRANCE