Upcoming Tradeshows, Conferences and Webinars

Name Date Time Location/Registration
Upcoming WebinarsDateTime


How to Maximize Power Savings in your RTL: Theory and PracticeMay 1310:00 AM PST

Register Now

DAC 2014June 2-49AM-6PM

Booth # 2333

Reaching for Maximum Power Reduction at RTL using PowerPro and SLECMonday                   Tuesday                   Wednesday11AM & 4PM                         12PM & 4PM                   10AM & 2PM

Monday: 11:00 AM  or  4:00 PM

Tuesday:  12:00 PM  or  4:00 PM

Wednesday: 10:00 AM  or  2:00 PM

Why and How to Adopt a High Level Synthesis and Verification MethodologyMonday                   Tuesday                   Wednesday1PM & 5PM                         3PM                                   3PM

Monday: 1:00 PM  or  5:00 PM

Tuesday:  3:00 PM

Wednesday: 3:00 PM

Leveraging High Level Synthesis to Achieve Low Power Designs: Catapult LPMonday                   Wednesday2PM                               11AM

Monday: 2:00 PM

Wednesday: 11:00 AM  

Cutting Through the Noise: A Practical Comparison between C++ and SystemC for High Level SynthesisTuesday                   Wednesday10AM                               1PM

Tuesday: 10:00 AM

Wednesday: 1:00 PM