• All features of Catapult^® SL plus low power optimization

• Built in C++/SystemC power estimation achieves up to 80% power reduction at the architecture level

• Sequential clock gating for fine grain power reduction of register, clock tree, and logic power

• Memory architecture optimization reduces memory power up to 80% with memory banking exploration and optimization

• Leverages Calypto’s^® leading PowerPro technology under the hood to seamlessly produce the low power RTL

• Provides SystemC/C++ power estimation

Catapult^® LP is the industry's first high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.

Catapult LP takes advantage of Calypto’s unique PowerPro^® technology by embedding it 'under the hood’ of Catapult to seamlessly produce the lowest power RTL and optimize designs at the architecture level where 80% of power decisions are made. For the first time, Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed loop PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by leveraging Calypto’s patented sequential analysis technology to deliver automatic fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings.