ABSTRACT

High-level synthesis (HLS) allows designers to synthesize different RTL architectures from C++ or SystemC electronicsystem level (ESL) models. The different hardware architectures are generated through user constraints, which specify such things as clock period, resource limitations, IO protocol and the level of desired concurrency. HLS has historically operated on two axis between performance and area. However, ESL is where the most significant power optimization can be achieved, which lead to the introduction of Calypto’s Catapult LP, enabling closed loop performance, area and power optimization at the hardware architecture level. Various low power techniques are used: bit-width optimization, multiple clock domain partitioning, memory access minimization, resource sharing, frequency exploration, power gating, and clock gating. Calypto’s low power HLS solution, Catapult LP, can implement all of these techniques automatically in the generated RTL starting from either C++ or SystemC.

This paper describes, in general, the Catapult® flow for exploring low power architectures, and it discusses in detail the low power optimization results achieved using the Catapult LP design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low power optimizations turned on. With low power optimizations on, Catapult uses the Calypto PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

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