Catapult Product Family Overview:

Catapult to SLECTraditional hardware design methods that require manual RTL development and debugging are too time consuming and error prone for today’s complex designs. The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level. From these high-level descriptions Catapult generates production quality RTL. With this approach, full hierarchical systems comprised of both control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time to RTL and automating the generation of bug free RTL, the Catapult significantly reduces the time to verified RTL. Catapult’s unified flow for modeling, synthesizing, and verifying complex ASICs and FPGAs allows hardware designers to fully explore micro-architecture and interface options. Advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for performance, area, and power.

Datasheets

* = User Information Required Before Download

Title Date Type Product Highlight
Catapult Product Family DatasheetOn-GoingDatasheetCatapult
Catware Library DatasheetOn-GoingDatasheetCatapult

White Papers

* = User Information Required Before Download

Title Date Type Product Highlight
*High Level Synthesis Report 2014November 2014White PaperCatapult

This is Calypto’s sixth annual High Level Synthesis survey report. 750 SoC, IC, and FPGA design professionals responded to the survey. This year's emphasis is on verification.

*Catapult LP for a Power Optimized ESL Hardware Realization FlowNovember 2012White PaperCatapult LP

This paper describes, in general, the Catapult® flow for exploring low power architectures, and it discusses in detail the low power optimization results achieved using the Catapult LP design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low power optimizations turned on. With low power optimizations on, Catapult uses the Calypto PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

*High-Level Synthesis Report 20112011White PaperCatapult

This report analyzes the survey results of 1,133 engineers and engineering managers and identifies relevant emerging trends.

*7 Steps to Higher Productivity: STMicroelectronics HLS Flow for Complex IPsDecember 2010White PaperCatapult

This paper covers STMicroelectronic’s project, where they wanted to have a completed video processor IP design in silicon in time for CES 2010, so they could fully demonstrate the 3D graphic capability of their latest SOC.

*Advanced Algorithmic Evaluation for Imaging, Communication and Audio Applications - Eigenvalue Decomposition Using The Catapult® Algorithmic Synthesis MethodologyWhite PaperCatapult

This paper discusses the hardware implementation of “eigenvalue decomposition”. Therefore, we developed two effective algorithms in ANSI C++ to obtain eigenvalues and synthesized them with Catapult Synthesis to compare the area versus the number of cycles at the algorithm level, respectively.

*Designing High Performance DSP Hardware Using Catapult C Synthesis and The Altera Accelerated LibrariesWhite PaperCatapult

This paper covers the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL.

Technical Papers

* = User Information Required Before Download

Title Date Type Product Highlight
High-Level Synthesis Blue BookTechnical PaperCatapult

This book provides a step-by-step approach to using C++ as a hardware design language, including an introduction to the basics of HLS using concepts familiar to RTL designers. Each chapter provides easy-to-understand C++ examples, along with hardware and timing diagrams where appropriate.

The book progresses from simple concepts such as sequential logic design to more complicated topics such as memory architecture and hierarchical sub-system design. Later chapters bring together many of the earlier HLS design concepts through their application in simplified design examples. These examples illustrate the fundamental principles behind C++ hardware design, which will translate to much larger designs. Although this book focuses primarily on C and C++ to present the basics of C++ synthesis, all of the concepts are equally applicable to SystemC when describing the core algorithmic part of a design.

On completion of this book, readers should be well on their way to becoming experts in high-level synthesis.

Data Types

* = User Information Required Before Download

Title Date Type Product Highlight
AC DatatypesJune 2014Data TypeCatapult

Algorithmic C (AC) datatypes are a class-based C++ library that provides arbitrary-length integer, fixed-point, floating-point and complex data types. They enable algorithm, system and hardware designers to precisely model bit-true behavior in C++ specifications while accelerating simulation speeds by 10-200x faster versus alternate datatypes.

*Modeling and Synthesizing Large Ratio Rate AdaptersApplication NoteData TypeCatapult

The file contains an example design and application note detailing the design of a 37/50 rate adaptor that can be applied to any large ratio rate conversion. It includes the appnote and source code example with a simple testbench.

HLS 5 Webinar's Code FilesJanuary 2014Data TypeCatapult

This zipped folder contains the code files that were used throughout the HLS 5 webinar "Optimizing SystemC/C++ Hardware Architectures Through HLS". The folder contains 3 files: "Decimator", "Filters", and "Windowing". Decimator contains an example of a regular compute-discard architecture and a polyphase implementation. Filters contains examples of FIR filter architectures: Classic, Folded, and Circular buffer. Windowing contains an example high performance (streaming one-pixel-per-clock-cycle) Sobel edge detector.

日本語版

* = User Information Required Before Download

Title Date Type Product Highlight
Catapult ファミリ データシートOn-Going日本語版Catapult
*CatapultとAltera社のAccelerated Libraryを使用した 高性能DSPハードウェア・デザインNovember 2013日本語版Catapult

従来のデザインフローは、C++のような高位言語でアルゴリズムの機能をモデル化し、これを手作業でRTLにコーディングしていました。この手作業によるRTL生成は時間がかかるだけでなく、エラーを発生しやすく、またバックエンドの配線遅延問題に影響を与えてしまいます。CatapultによるC++からの高位合成は、主にワイヤレス、ビデオ、画像処理など、非常に複雑で高い計算能力を必要とするアプリケーションで使用される、ASICハードウェア・サブシステムを構築するために使用されてきました。ASICで利用されてきたCatapultの機能とAltera社のAccelerated Libraryを組み合わせることにより、ANSI C++でモデル化したアルゴリズムから、FPGAハードウェア上で動作するように最適化されたRTLを迅速に生成することができます。さらに、このデザインフローを使用することで、C++からFPGA DSPブロックを直接生成し、高位合成制約を使用してバックエンドのタイミング問題を簡単に解決することが可能です。

*生産性向上のための7つのステップ: STMicroelectronics社の複雑なIPのための高位合成フローDecember 2010日本語版Catapult

この論文は、STMicroelectronicsがCES2010でシリコンの状態で完全なビデオIPとして希望し、また実際に完全な3Dグラフィックス機能のデモを行うことができたプロジェクトに関するものです

*AC DatatypesOctober 2012日本語版Catapult

カリプト社が無償で提供するビット 精度のC/C++データタイプです。g++やVisual C++でコンパイルでき、SystemC比最大200倍の高速性を生かし、語長や固定小数点最 適化を迅速に行えます。データ型としては、任意の語長の符号付き、符号なし整数型、固定小数点型タイプがあり、 CatapultとSLECによる高位合成フローでもサポートされています。

Videos

* = User Information Required Before Download

Screenshot Date Type Product Title & Highlight
May 2014VideoCatapult*How to Maximize the Verification Benefit of HLS - Webinar

RTL verification is a major challenge in today’s design flow, requiring huge amounts of resources to satisfactorily validate the RTL code. By raising the abstraction level design and verification is performed, and automating the RTL creation, High Level Synthesis (HLS) can reduce the RTL verification effort by 50%. This because the C++ or SystemC designs used in an HLS flow typically simulate 1,000-10,000 times faster than RTL. This webinar describes how to write a bit-accurate C++ design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL.

Topics we will be covering are:
• Types of high level models 
• How to write and debug a synthesizable C++ model
• Coverage driven verification in the context of high level synthesis

(Recorded Live 5/15/2014).

January 2014VideoCatapult*Optimizing SystemC/C++ Hardware Architectures Through HLS (HLS #5) - Webinar

Next to numerical precision, hardware architecture has the biggest impact on RTL quality generated by high level synthesis (HLS). In this 50 minute webinar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in HLS. Webinar will focus on C++ and SystemC code examples on different hardware architectures and the effect on the final implementation.

Topics we will be covering are:
Fundamental filter architectures
Delay line implementation and windowing for efficient image processing
(Recorded Live 01/14/14).
HLS 5 Webinar's Code Files: http://goo.gl/Gzk13f

November 2013VideoCatapult*How to Maximize the Verification Benefit of High Level Synthesis with SystemC (HLS #4) - Webinar

In this 50 minute webinar, Calypto will cover a verification approach that leverages SystemC simulation and High Level Synthesis (HLS) to reduce the RTL verification effort by 50%. The SystemC designs used in an HLS flow typically simulate 100-1,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. This webinar describes how to write a bit-accurate SystemC design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL. (Recorded Live 11/5/2013).

July 2013VideoCatapult*How to Maximize the Verification Benefit of High Level Synthesis with C++ (HLS #3) - Webinar

In this 50 minute webinar, Calypto will cover a verification approach that leverages C++ simulation and High Level Synthesis (HLS) to reduce the RTL verification effort by 50%.

The C++ designs used in an HLS flow typically simulate 1,000-10,000 times faster than RTL. This is because the interfaces and timing are specified in an abstract source. This webinar describes how to write a bit-accurate C++ design for HLS and how to use that model to improve specification functional coverage and avoid time-consuming debug at the RTL. (Recorded live 7/16/13).

March 2013VideoCatapult*How to Optimize for Power with High Level Synthesis (HLS #2) - Webinar
In this 50 minute webinar, Calypto will cover techniques to measure and reduce power in a High Level Synthesis (HLS) flow, starting from C++ or SystemC. 

For many designers, power optimization has become a key optimization target.  This webinar explains how moving to a more abstract source gives designers the ability to better optimize for power.  The webinar will cover both automated tool flows and manual techniques.  The automated tool flow focus on sequential clock gating, which uses both static state progression data and simulation vectors to disable registers that are not active.  The manual flow focuses on how to change the source code and HLS constraints to trade-off power with area, performance, and numerical precision. (Recorded Live 3/26/2013).

December 2012VideoCatapult*Comparing C++ to SystemC for HLS (HLS #1) - Webinar

A practical comparison between SystemC and C++ for High Level Synthesis

Have you ever wondered the difference between C++ and SystemC for high level synthesis (HLS)? This 50 minute webinar will provide a practical overview of the differences between the two most common ESL hardware description languages. The webinar will show side by side coding examples of the two languages for basic hardware concepts such as: hierarchy, IO, numerical precision and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult), Calypto is uniquely placed to discuss the differences between the two languages.

(Recorded Live 12/13/2012)

VideoCatapult*Catapult Control Logic Demo Using C++

Catapult Control Logic Demo Using C++.

VideoCatapult*Catapult Overview Demo Using C++

Catapult Overview Demo Using C++.

VideoCatapult*SystemC Synthesis Demo

Watch a demonstration of Catapult using SystemC.

VideoCatapult*Catapult Synthesis Primer: Technology Overview

This short video gives an overview of Catapult, explaining what it is, what it does and how design teams benefit from using it.

VideoCatapult*Catapult Synthesis: A Return on Investment Case Study

In this case study, Thomas Bollaert investigates a company's Return on Investment (ROI) for Catapult high level synthesis tool, and how they achieved a positive ROI within the first 12 months of Catapult usage.

VideoCatapult*Best Practices of HLS

In this primer, Shawn McCloud discusses best practices of high-level synthesis, and how the right coding style results in higher quality RTL and improved design reuse.

VideoCatapult*HLS Primer

In this interview, Shawn McCloud discusses high-level synthesis and the three major trends driving adoption of this technology in design teams around the world.