PowerPro Product Family Overview:
Automatic + Manually Assisted Power Optimization
- Comprehensive power optimization
reduces power by up to 60%
- Automatic power optimization
for clocks, memories, logic
and datapaths
- Fully automatic or guided manual
mode available
- Industry’s unique sequential formal verification verifies the optimized RTL
- Power analysis performed with either simulation based switching activity or verctor-less mode
- Advanced sequential analysis performs sequential clock gating
- Eliminates wasted dynamic and leakage memory power
Datasheets
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| Title | Date | Type | Product | Highlight |
|---|---|---|---|---|
| PowerPro Product Family Datasheet | On-Going | Datasheet | PowerPro |
White Papers
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| Title | Date | Type | Product | Highlight |
|---|---|---|---|---|
| *RTL Power Reduction & High Level Synthesis Report 2013 | May 2013 | White Paper | PowerPro | This report covers trends in the area of low power design and C based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends. |
| *Implementing an Efficient RTL Clock Gating Analysis Flow at AMD | January 2013 | White Paper | PowerPro | This paper provides an overview of how AMD used PowerPro to improve clock-gating efficiency, and shares the results and advantages of doing power analysis at the RTL stage rather than waiting until post-gate synthesis. |
| *Memory Power Reduction in SoC Designs Using PowerPro MG | White Paper | PowerPro MG | Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50-70% of the power dissipation. We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories. | |
| *Low Power RTL Report 2012 | April 2012 | White Paper | PowerPro CG | This report covers trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. |
| *Automating Sequential Clock Gating with PowerPro CG | White Paper | PowerPro CG | This paper describes sequential analysis and its application to clock gating. An example of sequential clock gating is given as well as a case study of reducing power in a digital signal correlation block using an automated RTL power optimization tool. | |
| *Power Optimization of a Configurable Video Platform using PowerPro™ CG | On-going | White Paper | PowerPro PA | With the proliferation of mobile multimedia devices, designers are challenged to provide the most advanced features to users while balancing the need to deliver the longest battery life possible. |
| *The PowerPro PowerAdviser flow: A Manual Use Mode for Applications that Require User Intervention | On-going | White Paper | PowerPro PA | PowerPro CG provides an automated solution to reduce this part of the design time to essentially cut it down to just machine runtime per block. In this paper, we describe a flow that enables two use models; one is to enable the use of PowerPro for designers who must meet very aggressive performance goals and would therefore prefer to optimize their RTL manually, and the other is to enable users of the automated PowerProCG flows to get even better results by providing hints based on sequential analysis. |
| *Utilizing Clock-Gating Efficiency to Reduce Power in RTL | White Paper | PowerPro CG | With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are gated. |
Case Studies
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| Title | Date | Type | Product | Highlight |
|---|---|---|---|---|
| *Reducing Power Consumption in a 20 million Gate Fiber Channel Switch SOC | Case Study | PowerPro CG | This case study covers a leading networking company’s validation of PowerPro CG results on two projects. Based on these successes, they have incorporated PowerPro CG into their low-power design SoC design flow. | |
| *Applying RTL Clock Gating to Reduce Power in Graphics Processors Chips | Case Study | PowerPro PA | This case study covers nVIDIA: “RTL power optimization is a critical step in our high-performance, low-power design methodology for PC graphics, visual computing and applications processors. PowerPro CG has shown substantial power savings on designs, including blocks already manually optimized for low power by RTL designers.” | |
| *PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations | Case Study | PowerPro PA | In this Texas Instrument case study, an interactive sequential analysis flow called PowerAdviser is introduced. The flow provides information to the user about redundant clock toggles where the automatic tool has not been able to identify a suitable clock gating condition to save power. | |
| *STARC Recommends PowerPro CG For RTL Power Optimization | Case Study | PowerPro CG | This case study discusses the evaluation criteria, process and results that led to the certification of PowerPro CG by STARC for its member companies. |
Technical Papers
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| Title | Date | Type | Product | Highlight |
|---|---|---|---|---|
| *DATE - PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations | March 2012 | Technical Paper | PowerPro PA | In this paper we present an interactive sequential analysis flow, PowerAdviser, which besides performing automatic sequential changes also provides information for additional power savings that the user realized through manual changes. Using this new flow they achieved dynamic power reduction up to 45% more than a purely automated flow. |
Videos
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| Screenshot | Date | Type | Product | Title & Highlight |
|---|---|---|---|---|
| April 2013 | Video | PowerPro | *Impact of Sequential Clock Gating on Design Flow and Verification - Webinar It is a well-known fact that sequential clock gating is more global in nature and offers more power savings over combinational clock gating. However, sequential clock gating is very complex as it involves temporal analysis over multiple clock cycles as well as examination of the stability, propagation, and observability of signal values. Trying to do sequential clock gating manually is extremely difficult, if not impossible, as it requires keeping track of data values over multiple cycles. Recently, new tools have come to the market that automate the analysis and insertion of sequential clock gating. However, since sequential clock gating can potentially change the behavior of flops and memories, it introduces new verification challenges. Traditional verification methodologies such as simulation are not effective and are too time consuming. Sequential formal verification may very well be the answer. In this webinar, Calypto will show the latest in sequential clock gating methodologies and its impact on the overall design flow. Latest sequential formal analysis, automated sequential clock gating, ECO and verification will be described. |
| February 2013 | Video | PowerPro MG | *Dynamic/Leakage Power Reduction in Memories (RTL #2) - Webinar In this webinar, Calypto will show how its patented sequential analysis technology can be applied to reduce memory power. Deep sequential analysis examines the read and write operation of memories over several cycles and automatically optimizes the memories for both dynamic and leakage power. It also implements optimized sleep modes for the memory. (Recorded Live 02/12/2013) |
| December 2012 | Video | PowerPro | *Minimizing RTL Power Through Sequential Analysis (RTL #1) - Webinar A Webinar on the Latest Techniques for Power Optimization at RTL In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webinar will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization. (recorded live 12/04/12) |