SLEC: Product Family Overview

SLEC integrated into Existing Flows

The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular. On the other end of the spectrum, the need to create faster and lower power RTL designs for consumer devices has led to design flows where designers use aggressive techniques for optimizing a given RTL design. However these new design techniques create new challenges for verification. There is a significant need for next generation equivalence checking solutions which verify software models against the HLS generated RTL, as well as various optimized versions of an RTL design against the original RTL. Traditional combinational equivalence techniques are not applicable to these next generation problems.

Datasheets

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Title Date Type Product Highlight
SLEC Product Family DatasheetOn-GoingDatasheetSLEC

White Papers

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Title Date Type Product Highlight
*Integrating Sequential Logic Equivalence Checking with the Cadence C-to-Silicon FlowOn-goingWhite PaperSLEC HLS

Specific emphasis is placed on the integration between SLEC and Cadence C to Silicon Compiler (CtoS).

*Sequential Equivalence Checking: A New Approach to Functional verification of Datapath and Control Logic ChangesWhite PaperSLEC RTL

This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.

*RTL Verification Without TestbenchesWhite PaperSLEC RTL

Sequential equivalence checking technology reduces testbench requirements, improving productivity and giving designers more opportunities to optimize their RTL designs. This paper traces the development of a DES encryption design to demonstrate the advantages of doing RTL verification without testbenches.

Case Studies

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Title Date Type Product Highlight
*Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence CheckingCase StudySLEC

This case study describes the system-level design flow of a commercial graphics processing chip. In this flow, system models are developed to validate the arithmetic computation of video instructions and then used verify the RTL implementation using SLEC.

Technical Papers

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Title Date Type Product Highlight
*DATE - A Semi-Canonical Form for Sequential AIGsFebruary 2013Technical PaperSLEC Product Family Overview

Calypto collaborated with UC Berkeley to develop an innovative way to detect isomorphisms within logic designs. Our work, presented in DATE 2013, describes a way to use simulation to quickly identify isomorphisms. 

日本語版

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Title Date Type Product Highlight
SLEC ファミリ データシートOn-Going日本語版SLEC