SLEC Pro:

SLEC Pro FlowBenefits of SLEC Pro


● Comprehensive verification of PowerPro results

 

● 100% test coverage of all clock gating enable conditions

 

● Integrated flow with PowerPro to improve verification productivity

 

● Eliminates the need for clock gating specific testbench development

 

● Replaces time consuming simulation regressions with fast results

 

● Isolates bugs quickly with short, concise debug waveforms

 

SLEC Pro formally verifies PowerPro power optimizations.

Based on Calypto's patented Sequential Analysis Technology, SLEC Pro provides efficient, comprehensive verification of PowerPro optimized RTL.

 

SLEC Pro formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC Pro does not require one to one mapping of registers.

 

SLEC Pro confirms that no functional errors exist in any of the clock-gating enable conditions added or modified by PowerPro or generates short, concise waveforms that pinpoint design differences. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user's native debugging environment.

 

SLEC Pro is seamlessly integrated into the PowerPro design flow to remove the need for users to specify design files and setup.

 

SLEC Pro is part of Calypto's SLEC family of proven sequential equivalence checking products.

Datasheets

* = User Information Required Before Download

Title Date Type Product Highlight
SLEC Product Family DatasheetOn-GoingDatasheetSLEC

White Papers

* = User Information Required Before Download

Title Date Type Product Highlight
*Integrating Sequential Logic Equivalence Checking with the Cadence C-to-Silicon FlowOn-goingWhite PaperSLEC HLS

Specific emphasis is placed on the integration between SLEC and Cadence C to Silicon Compiler (CtoS).

*Sequential Equivalence Checking: A New Approach to Functional verification of Datapath and Control Logic ChangesWhite PaperSLEC RTL

This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.

*RTL Verification Without TestbenchesWhite PaperSLEC RTL

Sequential equivalence checking technology reduces testbench requirements, improving productivity and giving designers more opportunities to optimize their RTL designs. This paper traces the development of a DES encryption design to demonstrate the advantages of doing RTL verification without testbenches.

Case Studies

* = User Information Required Before Download

Title Date Type Product Highlight
*Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence CheckingCase StudySLEC

This case study describes the system-level design flow of a commercial graphics processing chip. In this flow, system models are developed to validate the arithmetic computation of video instructions and then used verify the RTL implementation using SLEC.

Technical Papers

* = User Information Required Before Download

Title Date Type Product Highlight
*DATE - A Semi-Canonical Form for Sequential AIGsFebruary 2013Technical PaperSLEC Product Family Overview

Calypto collaborated with UC Berkeley to develop an innovative way to detect isomorphisms within logic designs. Our work, presented in DATE 2013, describes a way to use simulation to quickly identify isomorphisms. 

日本語版

* = User Information Required Before Download

Title Date Type Product Highlight
SLEC ファミリ データシートOn-Going日本語版SLEC