SLEC HLS:

SLEC HLS FlowBenefits of SLEC HLS

● Independent verification of high level synthesis results

 

● Reduces project risk by identifying ambiguities between system and RTL languages

 

● Verifies RTL blocks without waiting for the entire assembled design

 

● Supports Forte Modular Interfaces and Mentor Algorithm C (TM) datatypes

 

● Replaces time consuming simulation regressions with fast results

 

● Isolates bugs quickly with short, concise debug waveforms

 

 

SLEC HLS comprehensively verifies the RTL generated by High Level Synthesis (HLS) tools. Based on Calypto’s patented Sequential Analysis Technology, SLEC HLS eliminates functional errors in High Level Synthesis (HLS) generated RTL. 

 

SLEC HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. Unlike combinational equivalence checkers, SLEC System-HLS does not require one to one mapping of registers. SLEC HLS increases design productivity through automated setup and elimination of block-level RTL simulation.

 

SLEC HLS either confirms that no functional errors exist or generates short, concise waveforms that pinpoint design bugs. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user’s native debugging environment. SLEC HLS is part of Calypto’s SLEC family of proven sequential equivalence checking products. SLEC HLS provides a seamless link with Cadence and Forte HLS tools and requires a SLEC license.

Datasheets

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Title Date Type Product Highlight
SLEC Product Family DatasheetOn-GoingDatasheetSLEC

White Papers

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Title Date Type Product Highlight
*Integrating Sequential Logic Equivalence Checking with the Cadence C-to-Silicon FlowOn-goingWhite PaperSLEC HLS

Specific emphasis is placed on the integration between SLEC and Cadence C to Silicon Compiler (CtoS).

*Sequential Equivalence Checking: A New Approach to Functional verification of Datapath and Control Logic ChangesWhite PaperSLEC RTL

This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.

*RTL Verification Without TestbenchesWhite PaperSLEC RTL

Sequential equivalence checking technology reduces testbench requirements, improving productivity and giving designers more opportunities to optimize their RTL designs. This paper traces the development of a DES encryption design to demonstrate the advantages of doing RTL verification without testbenches.

Case Studies

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Title Date Type Product Highlight
*Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence CheckingCase StudySLEC

This case study describes the system-level design flow of a commercial graphics processing chip. In this flow, system models are developed to validate the arithmetic computation of video instructions and then used verify the RTL implementation using SLEC.

Technical Papers

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Title Date Type Product Highlight
*DATE - A Semi-Canonical Form for Sequential AIGsFebruary 2013Technical PaperSLEC Product Family Overview

Calypto collaborated with UC Berkeley to develop an innovative way to detect isomorphisms within logic designs. Our work, presented in DATE 2013, describes a way to use simulation to quickly identify isomorphisms. 

日本語版

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Title Date Type Product Highlight
SLEC ファミリ データシートOn-Going日本語版SLEC