• RTL level power analysis with gate-level accuracy
  • Reduces total power by up to 60%
  • Automatic sequential clock gating
  • Optimizes memory power usage
  • Eliminates wasted dynamic and leakage power
  • Supports both manual and automated optimization
  • Fully verified RTL without the need for simulation

PowerPro Product Family Overview

PowerPro CG

PowerPro MG

PowerPro PA

RTL Power Optimization Webinar

Low Power for Memory Webinar

Sequential Verification Webinar


  • SystemC or C++ to create verified, power-ready RTL
  • Maximum impact on power usage
  • Correct-by-construction design
  • Error free RTL generation
  • Supports cycle accurate and transaction level modeling
  • Production proven with several tapeouts
  • Certified in TSMC reference flow 11

Catapult 8 Platform

Catapult Product Family Overview

Catapult SL

Catapult LP

Catware Library

Catapult LP White Paper

HLS Webinars


  • Leverages system level models to verify RTL designs
  • Verifies RTL blocks without waiting for entire design completion
  • Replaces time consuming simulation
  • Finds functional errors that are difficult to detect with simulation
  • Verifies RTL without the need for complex testbenches
  • Isolate bugs quickly with short concise debug waveforms
  • Reduces project risks by identifying ambiguities between system and RTL design

SLEC Product Family Overview