Qualcomm has successfully applied their HLS/HLV flow and Calypto’s HLS/HLV technology on a wide range of video and image processing IP designs including IPs which were integrated into flagship smartphone applications. Proving the usefulness of HLS/HLV across many design styles, these IP blocks range in size and complexity from small and simple to large and complex; from small data bandwidth compression blocks, with tight feedback loops, instantiated in many places on a chip to large subsystems implementing very complicated logic.  


For more information see the white paper Designing ASIC IP at Higher Level of Abstraction

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